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How does superconducting logic process information?

IARPA describes superconducting Josephson junctions as fast, low-energy switches operating at cryogenic temperatures, while its C3 program identifies memory and integration as obstacles to complete systems [1].

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A switch built from a Josephson junction

IARPA describes a Josephson junction as a superconducting switching device that can change state in about one picosecond and dissipate less than 10 to the minus 19 joules per switch [1]. IARPA's figures describe switching at the device level, rather than the electricity consumed by a complete computer and its refrigerator [1]. The IEEE ISCAS paper explains that a junction has a critical current associated with the transition between zero and nonzero voltage [5]. IEEE ISCAS explains that bias current must be chosen carefully to keep the circuit operating as intended [5].

IEEE ISCAS describes niobium interconnects in rapid single flux quantum circuits operating at 4.2 kelvin, commonly using liquid helium for cooling [5]. IEEE ISCAS focuses on switches and signals inside a circuit, rather than power delivery over a distance [5]. IARPA's C3 program also treats the junction as one part of a larger computing problem that includes memory, integration density, and complete systems [1]. IARPA's system challenges show why a low-energy switch alone does not establish a low-energy computer [1].

What a single flux quantum pulse carries

IEEE ISCAS explains that magnetic flux in a superconducting loop is quantized and that rapid single flux quantum logic represents information using brief voltage pulses [5]. In the IEEE ISCAS paper's clocked example, the presence or absence of a pulse during a clock period represents a digital value [5]. IEEE ISCAS gives the time integral of the voltage pulse as one magnetic flux quantum, approximately 2.07 millivolt picoseconds [5]. IEEE ISCAS associates the pulse with a 2-pi change in the superconducting phase difference across a junction [5].

IEEE ISCAS describes gates made from superconducting loops that can store a flux quantum or leave a loop without one, depending on the circuit function [5]. IEEE ISCAS also describes Josephson transmission lines, where a chain of junctions regenerates and passes pulses between circuit elements [5]. IEEE ISCAS distinguishes these active lines from passive transmission lines [5]. The IEEE ISCAS account describes a controlled signal with a defined voltage-time area; it does not claim that an entire processor consumes zero power [5].

RSFQ and the cost of keeping gates biased

IEEE ISCAS calls rapid single flux quantum, or RSFQ, a logic family built from Josephson junctions and superconducting interconnects [5]. IEEE ISCAS explains that its junctions need appropriate bias currents to switch correctly, and its conventional bias network uses resistors to distribute and regulate those currents [5]. Scientific Reports explains that these resistors produce static power dissipation, which grows as a circuit expands [4]. As IEEE ISCAS describes static dissipation as distinct from switching power, switching energy alone leaves out an important part of the budget [5].

IEEE ISCAS reports an example in which static resistor dissipation is roughly 60 times the dynamic power associated with junction switching [5]. The IEEE ISCAS ratio belongs to the paper's circuit assumptions, rather than every possible implementation [5]. IEEE ISCAS explains that superconducting wires in the bias network can carry current without the distributed resistance of ordinary wires, while the bias resistors still dissipate power at the cells [5]. The IEEE ISCAS account shows why superconducting wiring does not remove the need to account for deliberately resistive circuit elements [5].

ERSFQ changes how bias reaches the gates

IEEE ISCAS describes energy-efficient RSFQ, or ERSFQ, as a way to replace conventional dissipative bias resistors with Josephson junctions and superconducting inductors [5]. In the IEEE ISCAS description, the existing RSFQ gate library can remain unchanged while the bias distribution changes [5]. IEEE ISCAS says this removes the static dissipation associated with those bias resistors, but the added circuit elements still require design and consume resources during operation [5]. The IEEE ISCAS account describes a different biasing approach, not a guarantee that all chip or system losses vanish [5].

IEEE ISCAS identifies current ripple, bias margins, physical area, and dynamic power as linked design constraints in ERSFQ networks [5]. IEEE ISCAS explains that larger inductors can reduce current variations but occupy significant area, while a feeding Josephson transmission line helps establish a voltage reference for the bias bus [5]. The IEEE ISCAS paper's proposed guidelines draw on circuit simulations to study these tradeoffs [5]. The IEEE ISCAS simulations support design choices for bias networks; they do not by themselves establish the energy use of a finished commercial computer [5].

AQFP takes a different route to low energy

Scientific Reports describes adiabatic quantum-flux-parametron, or AQFP, logic as another superconducting logic family, using alternating excitation currents as both clock and power supply [4]. Scientific Reports explains that gradual, adiabatic switching can reduce dynamic dissipation and address the direct-current bias overhead of conventional RSFQ [4]. In Superconductor Science and Technology, Takeuchi and colleagues report correct operation of three fabricated stages of niobium AQFP NOT gates [6]. Superconductor Science and Technology estimates the designed gate's dynamic dissipation at 12% of the product of critical current and flux quantum for a 1,000-picosecond rise or fall time [6].

Scientific Reports presents a synthesis and energy-estimation study of 18 AQFP benchmark circuits and compares them with semiconductor cell libraries [4]. Scientific Reports forecasts a maximum 9,313-fold reduction in energy per clock cycle against the selected 12-nanometer FinFET library, under its modeled comparison [4]. Scientific Reports identifies its AQFP estimates as synthesis results based on circuit energy models, rather than a measurement of an entire cooled computer [4]. Scientific Reports also explains that AQFP buffers are needed to synchronize data across logic levels, making the clocking scheme part of the circuit design [4].

Cooling, memory, and the path to systems

IARPA's C3 page presents studies estimating a superconducting computer at one quadrillion floating-point operations per second for about 25 kilowatts, including its cryogenic cooler [1]. IARPA labels that figure as a study estimate and says proof at smaller scales is essential before attempting a supercomputer [1]. Cooling is a system input: IARPA's estimate includes the refrigerator, while IEEE ISCAS describes circuits operating at 4.2 kelvin [1][5]. IARPA's system challenges and imec's integration research indicate why a meaningful comparison needs a stated workload and system boundary, including cooling, memory, interfaces, and supporting electronics [1][3].

IARPA identifies limited memory, integration density, and the absence of complete computing systems as challenges for its C3 program [1]. IARPA says its SuperTools program sought automated design and analysis tools, including cell libraries and process design kits, with a design-tool goal of at least 10 million junctions or one million logic gates [2]. IARPA's stated goal concerns tool capability, not proof of a working processor at that scale [2]. Imec describes research spanning materials, fabrication, logic, memory, packaging, and system architecture, illustrating how much remains to be integrated around the switch [3].

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